Silicon Labs PCI Express Gen 4 Clock Sets New Performance Benchmarks for Data Center and Consumer Product Design

Silicon Labs (also known as "Coretech") announced a series of industry's lowest jitter, highest integration, lowest power clock generator products for PCI Express® (PCIe®) Gen 1/2/3/4 applications. . Developers can now confidently design a PCIe-compliant solution using Silicon Labs PCIe clocks, and get maximum jitter margins and reduce product development risk.

Internal power supply filtering prevents power supply noise from degrading clock jitter performance, reducing the number of devices and footprint by 30% compared to competing solutions.

Developers designing battery-powered applications (such as digital cameras) pay special attention to power consumption. The 2-output Si52202 clock is optimized for low-power 1.5-1.8V applications, providing the industry's lowest power for PCIe applications. It is available in a small 3mm x 3mm 20-QFN package and features 45% smaller device size than competing solutions.

James Wilson, senior marketing director of clock products at Silicon Labs, said: “Silicon Labs continues to promote the innovation, performance and integration of PCI Express clocks. With the release of the Si522xx family, we can now fully meet the needs of the entire PCIe application, covering both server and storage. To industrial and consumer applications."

Relevant Si52 series products

Author：Brittany Antonia （The author of article owns the copyright.）