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UPD74HC373GS

Part No UPD74HC373GS
Manufacturer NEC
Catalog Electronic Wholesale
Sample
Rohs State Need to verify
ECAD Module
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Reference Date Code 02/P
Reference case SOP
Manufacturer NEC
Manufacturer Homepage www.nec.com/
RoHS State Request Verification
Win Source Part Number 757849-UPD74HC373GS
Popularity Low
Supply and Demand Status Balance
Ultra Librarian 3D Model Ultra Librarian UPD74HC373GS CAD Model

Description

The UPD74HC373GS is a high-speed silicon gate CMOS octal D-type transparent latch manufactured by NEC. It features a three-state output and is designed for use in high-performance memory and microprocessor systems. This device is part of the 74HC series, known for its high speed and low power consumption compared to earlier TTL logic families.

Applications

  • Address latches for microprocessor systems
  • Data buffers
  • Memory address decoding
  • Output ports for microcontrollers
  • Parallel-to-serial converters

Features

  • High-speed operation: tpd = 11 ns (typ.) at VCC = 5 V
  • Low power dissipation: ICC = 4 μA (max) at VCC = 5 V
  • Wide operating voltage range: VCC = 2 V to 6 V
  • Three-state outputs for bus interface
  • Fanout of 10 LSTTL loads
  • Positive edge-triggered D-type latches

Benefits

  • Improved system performance due to high-speed operation
  • Reduced power consumption, extending battery life in portable devices
  • Compatibility with a wide range of power supply voltages
  • Easy integration into bus-oriented systems
  • High drive capability for interfacing with multiple devices
  • Simple data storage using transparent latch functionality

Additional Details

The UPD74HC373GS is available in a surface-mount package. It provides eight transparent latches, each with a D-type input and a three-state output. When the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched and retain the last data present before the transition. The output enable (OE) input controls the three-state outputs; when OE is low, the outputs are enabled, and when OE is high, the outputs are in a high-impedance state.

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