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74HCT7273D,118

Part No 74HCT7273D,118
Manufacturer NXP / Nexperia
Catalog Logic - Flip Flops
Description IC D-TYPE POS TRG SNGL 20SOIC
Datasheet
Sample
Rohs State rohs
ECAD Module
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Categories Integrated Circuits
Manufacturer NXP
Packaging Reel - TR
Status Obsolete(EOL)
Purpose Master Reset
Type D-Type
Output Type Non-Inverted
Number of Elements 1
Number of Bits per Element 8
Max Frequency 56MHz
Max Propagation Delay @ V, Max CL 30ns @ 4.5V, 50pF
Trigger Type Positive Edge
Current - Output High, Low -, 4mA
Supply Voltage - Operating 4.5 V to 5.5 V
Current - Quiescent 8μA
Input Capacitance 3.5pF
Temperature Range - Operating -40°C to 125°C (TA)
Mounting SMD (SMT)
Dimension 20-SOIC (0.295", 7.50mm Width)
Win Source Part Number 119357-74HCT7273D,118
Popularity Medium
Supply and Demand Status Balance
Ultra Librarian 3D Model Ultra Librarian 74HCT7273D,118 CAD Model

Description

Product Overview: 74HCT7273D,118 from NXP Semiconductors

The 74HCT7273D,118 is a high-quality integrated circuit from NXP Semiconductors, renowned for its precision and reliability in digital electronics. This particular product is part of the 74HCT series, which is compatible with TTL levels and known for its high noise immunity and low power consumption. The 74HCT7273D,118 is designed to meet the rigorous demands of a wide range of applications, from industrial and commercial to consumer electronics.

Key Features

  • Logic Type: Latch
  • Output Type: Tri-State
  • Number of Elements: 8
  • Number of Bits per Element: 1
  • Supply Voltage Range: 4.5V to 5.5V
  • Logic Case Style: SOIC
  • No. of Pins: 20
  • Operating Temperature Range: -40°C to +125°C
  • Mounting Type: Surface Mount

Product Description

The 74HCT7273D,118 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HCT7273D,118 features eight edge-triggered, D-type flip-flops with individual D inputs and O outputs. The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously.

The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the D input is transferred to the corresponding flip-flop's O output on the LOW-to-HIGH transition of CP. A HIGH on MR clears all flip-flops, forcing all O outputs LOW, independent of the state of CP. When MR is LOW, data can be entered into the device regardless of the state of CP.

All outputs have the same source and sink capability. When the output enable (OE) input is LOW, the outputs are in the normal logic state; when OE is HIGH, the outputs are in the high-impedance OFF-state. This state is used for data bus interfacing and multiplexing. The device's balanced propagation delays and transition times across all input and output pins provide significant advantages in designing high-speed, reliable digital systems.

Applications

  • Data storage and retrieval
  • Bus interface and driver
  • Data multiplexing
  • Industrial control systems
  • Instrumentation and measurement systems

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Pricing & Ordering

Quantity Unit Price Ext. Price
150+ $0.3927 $58.9050
360+ $0.3222 $115.9920
560+ $0.3119 $174.6640
770+ $0.3015 $232.1550
990+ $0.2922 $289.2780
1,325+ $0.2622 $347.4150
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Availability: 3,701 pieces
MOQ: 150 pcs
Order Increment : 1 pcs
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